compound_ports
CompoundPort
Bases: Port
Aggregate different ports into one structure (like a struct) by subclassing this.
Examples:
Combining data/clk into one Port instance.
Attributes:
Name | Type | Description |
---|---|---|
sym_table |
SymbolTable
|
Hold all the mappings |
Source code in circuitbrew/compound_ports.py
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|
__init__(name='')
_insert_into_instance(instance)
Used for the descriptor protocol for attribute access to the sub ports.
Returns:
Name | Type | Description |
---|---|---|
CompoundPort | Either the lookup if it exists, or the newly created self |
Source code in circuitbrew/compound_ports.py
E1of2
Bases: CompoundPort
A dual rail port with enable.
For simulation, we will do a quick hack to make sure that we don't need to handle the data wires and enable individually. The async queues already give us all the back-pressure behavior we need. We will send the data value on the true rail only, and ignore the f and e rails.
Attributes:
Name | Type | Description |
---|---|---|
t |
Port
|
True rail |
f |
Port
|
False rail |
e |
Port
|
Enable (active low acknowledge) |
Source code in circuitbrew/compound_ports.py
recv()
async
E1of2InputPort
E1of2OutputPort
SupplyPort
Bases: CompoundPort
Use this for passing around the vdd and gnd global ports
Attributes:
Name | Type | Description |
---|---|---|
vdd |
Port
|
|
gnd |
Port
|
|