Skip to content

qdi

Celement2

Bases: Module

A two-input Muller C-element

Source code in circuitbrew/qdi.py 
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
class Celement2(Module):
    """ A two-input Muller C-element
    """
    i = InputPorts(width=2)
    o = OutputPort()
    p = SupplyPort()

    def build(self):
        """ build method
        """
        p = self.p
        # Let's constnnruct this using combination feedback
        pdn = self.i[0] & self.i[1]
        pup = ~self.i[0] & ~self.i[1]

        self.inv = Inv(out = self.o, p = p)
        _o = self.inv.inp

        cf_pdn = self.o & (self.i[0] | self.i[1])
        cf_pup = ~self.o & (~self.i[0] | ~self.i[1])

        self.celem = self.make_stacks(output=_o, pdn=pdn, pup=pup, power=p)
        self.cf    = self.make_stacks(output=_o, pdn=cf_pdn, pup=cf_pup, power=p)

        self.finalize()

    async def sim(self):
        """ Sim method
        """
        self.current_val = 0
        while True:
            #val = await self.i[0].recv()
            val = []
            for i in range(2):
                val.append(await self.i[i].recv())
            if val[0] == val[1]:
                self.current_val = val[0]
            await self.out.send(self.current_val)

build()

build method

Source code in circuitbrew/qdi.py 
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
def build(self):
    """ build method
    """
    p = self.p
    # Let's constnnruct this using combination feedback
    pdn = self.i[0] & self.i[1]
    pup = ~self.i[0] & ~self.i[1]

    self.inv = Inv(out = self.o, p = p)
    _o = self.inv.inp

    cf_pdn = self.o & (self.i[0] | self.i[1])
    cf_pup = ~self.o & (~self.i[0] | ~self.i[1])

    self.celem = self.make_stacks(output=_o, pdn=pdn, pup=pup, power=p)
    self.cf    = self.make_stacks(output=_o, pdn=cf_pdn, pup=cf_pup, power=p)

    self.finalize()

sim() async

Sim method

Source code in circuitbrew/qdi.py 
37
38
39
40
41
42
43
44
45
46
47
48
async def sim(self):
    """ Sim method
    """
    self.current_val = 0
    while True:
        #val = await self.i[0].recv()
        val = []
        for i in range(2):
            val.append(await self.i[i].recv())
        if val[0] == val[1]:
            self.current_val = val[0]
        await self.out.send(self.current_val)

VerilogBucketE1of2

Bases: VerilogParametrizedModule

Dual-rail with enable (E1of2) output sink/verification for 4-phase QDI circuits

Source code in circuitbrew/qdi.py 
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
class VerilogBucketE1of2(VerilogParametrizedModule):
    """ Dual-rail with enable (E1of2) output sink/verification for 4-phase QDI circuits
    """
    _pReset = InputPort()
    _sReset = InputPort()
    l = E1of2InputPort()


    def __init__(self, name, values=None, **kwargs):
        super().__init__(name=name, **kwargs)
        self.values = values
        self.src_filename = {'hspice': 'hspice_bucket_1of2.va'}

    def get_spice(self):
        simtype = self.sim_setup['sim_type']
        src_filename = self.src_filename[simtype]
        param_dict = {'values': self.values,
                      'nvalues': len(self.values), 
                      'MODULE_NAME': self.get_module_type_name(),
                     }
        output_filename = f'template_{self._id}_{src_filename}'

        self._emit_src_file(src_filename, param_dict, output_filename)

        l = [f'.hdl {output_filename}']
        return l


    async def sim(self):
        """ Sim method """
        if self.values:
            return # No need to sim as user supplied values

        try:
            logger.info(f'Bucket_1of2 {self} waiting')
            vals = []
            while True:
                val = await self.l.recv()
                logger.info(f'Bucket_1of2 {self} received {val}')
                vals.append(val)
        except curio.CancelledError:
            pass # Time to end because the simulation is done and we were cancelled
        finally:
            # Save the check values for writing to a file
            self.values = vals

sim() async

Sim method

Source code in circuitbrew/qdi.py 
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
async def sim(self):
    """ Sim method """
    if self.values:
        return # No need to sim as user supplied values

    try:
        logger.info(f'Bucket_1of2 {self} waiting')
        vals = []
        while True:
            val = await self.l.recv()
            logger.info(f'Bucket_1of2 {self} received {val}')
            vals.append(val)
    except curio.CancelledError:
        pass # Time to end because the simulation is done and we were cancelled
    finally:
        # Save the check values for writing to a file
        self.values = vals

VerilogSrcE1of2

Bases: VerilogParametrizedModule, SourceModule

Dual-rail with enable (E1of2) input source for 4-phase QDI circuits

Source code in circuitbrew/qdi.py 
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
class VerilogSrcE1of2(VerilogParametrizedModule, SourceModule):
    """ Dual-rail with enable (E1of2) input source for 4-phase QDI circuits
    """
    _pReset = InputPort()
    _sReset = InputPort()
    l = E1of2OutputPort()


    def __init__(self, name, values, **kwargs):
        super().__init__(name=name, **kwargs)
        self.values = values
        self.src_filename = {'hspice': 'hspice_src_1of2.va'}

    def get_spice(self):
        simtype = self.sim_setup['sim_type']
        src_filename = self.src_filename[simtype]
        param_dict = {'values': self.values,
                      'nvalues': len(self.values), 
                      'MODULE_NAME': self.get_module_type_name(),
                     }
        output_filename = f'template_{self._id}_{src_filename}'

        self._emit_src_file(src_filename, param_dict, output_filename)

        l = [f'.hdl {output_filename}']
        return l

    async def sim(self):
        for val in self.values:
            await self.l.send(val)

Wchb

Bases: Module

A QDI weak-conditioned-half-buffer using 4-phase 1-bit data

Source code in circuitbrew/qdi.py 
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
class Wchb(Module):
    """ A QDI weak-conditioned-half-buffer using 4-phase 1-bit data
    """
    l = E1of2InputPort()
    r = E1of2OutputPort()
    _pReset = InputPort()
    p = SupplyPort()

    def build(self):
        """ Build method """
        self.c2_t = Celement2(i=[self.l.t, self.r.e], o = self.r.t, p=self.p)
        self.c2_f = Celement2(i=[self.l.f, self.r.e], o = self.r.f, p=self.p)
        self.inv_mypreset = Inv(inp=self._pReset, p=self.p)
        mypreset = self.inv_mypreset.out

        self.nor = Parameterize(NorN, N=3)(a=[self.r.t, self.r.f, mypreset], 
                                           b=self.l.e, p=self.p)
        self.finalize()

    async def sim(self):
        """ Sim method """
        while True:
            logger.debug(f'{self} Waiting to receive')
            val = await self.l.recv()
            logger.debug(f'{self} received {val}')
            await self.r.send(val)
            logger.debug(f'{self} sent {val}')

build()

Build method

Source code in circuitbrew/qdi.py 
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
def build(self):
    """ Build method """
    self.c2_t = Celement2(i=[self.l.t, self.r.e], o = self.r.t, p=self.p)
    self.c2_f = Celement2(i=[self.l.f, self.r.e], o = self.r.f, p=self.p)
    self.inv_mypreset = Inv(inp=self._pReset, p=self.p)
    mypreset = self.inv_mypreset.out

    self.nor = Parameterize(NorN, N=3)(a=[self.r.t, self.r.f, mypreset], 
                                       b=self.l.e, p=self.p)
    self.finalize()

sim() async

Sim method

Source code in circuitbrew/qdi.py 
102
103
104
105
106
107
108
109
async def sim(self):
    """ Sim method """
    while True:
        logger.debug(f'{self} Waiting to receive')
        val = await self.l.recv()
        logger.debug(f'{self} received {val}')
        await self.r.send(val)
        logger.debug(f'{self} sent {val}')